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DATA SHEET
MOS INTEGRATED CIRCUIT
PD98405
155M ATM INTEGRATED SAR CONTROLLER
DESCRIPTION
The PD98405 (NEASCOT-S20TM) is a high-performance SAR chip that performs segmentation and reassembly of ATM cells. It has a PCI bus interface, a SONET/SDH 155-Mbps framer, and a clock recovery circuit and supports an ABR function in hardware. The PD98405 conforms to ATM Forum and has the functions of the AAL-5 SAR sublayer, ATM layer, and TC sublayer.
FEATURES
* Conforms to ATM Forum. * Host bus interface supporting PCI bus/generic bus. PCI interface (5/3.3 V, 32/64 bits, 33 MHz): Conforms to PCI Specification 2.1 Generic bus interface (5/3.3 V, 32 bits, 33 MHz)
* AAL-5 SAR sublayer, ATM layer, and TC sublayer functions * Hardware support of AAL-5 processing * Software support of non-AAL-5 traffic * SONET STS-3c/SDH STM-1 155-Mbps framer function * Clock recovery/clock synthesizer function * Supports up to 32 K virtual channels (VCs) * Sixteen traffic shapers for VBR for transmission scheduling * Hardware support of CBR/VBR/ABR/UBR service * Supports multi-cell burst transfer for transmission and reception * MIB counter function * Supports LAN emulation function * Receive FIFO of 96 cells * External PHY devices connectable: UTOPIA Level-1 interface * 0.35-m CMOS process, +5-/3.3-V power supply Bus interface +5 V: +5-/3.3-V power supply Bus interface +3.3 V: +3.3-V power supply
* 304-pin plastic QFP
ORDERING INFORMATION
Part Number Package 304-pin plastic QFP (0.5-mm fine pitch) (40 x 40 mm)
PD98405GL-PMU
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S12689EJ2V0DS00 (2nd edition) Date Published April 1999 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1997, 1999
PD98405
SYSTEM CONFIGURATION EXAMPLE
ATM Interface Card
Rx PMD Control memory
PD98405
ATM network
Tx Expansion ROM EEPROMTM
PCI bus
2
Data Sheet S12689EJ2V0DS00
BLOCK DIAGRAM
UTOPIA interface
Receive data FIFO (96 cells) Receive PHY interface Receive controller Receive ATM interface & FIFO (4 cells) Receive framer
DMA output block
PMD
PMD interface & Clock recovery & Clock synthesizer
Host system
Sequencer Control memory interface Transmit controller Transmit PHY interface Transmit data FIFO (10 cells)
PCI interface
Host command FIFO (10 commands)
Control interface
Data Sheet S12689EJ2V0DS00
DMA input block
Transmit ATM interface & FIFO (4 cells)
Transmit framer
DMA block Transmit queue buffer (64 cells)
Control memory
PD98405
3
PD98405
OUTLINE OF PINS
304-pin plastic QFP (0.5-mm fine pitch) (40 x 40 mm)
304 229 228 1 JTAG PMD PHY device EEPROM
Expansion ROM
PD98405GL-PMU
PCI
Control memory 76 77 152 153
4
Data Sheet S12689EJ2V0DS00
PD98405
PIN NAME
ABRT_B ACK64_B AD63-AD0 AGND ASEL_B ATTN_B AVDD3 BE3_B-BE0_B CA18-CA0 CBE3_B-CBE0_B CD31-CD0 CLK COE_B CPAR3-CPAR0 CWE_B DEVSEL_B DR/W_B EMPTY_B/RCLAV ERR_B E2PCLK E2PCS E2PDI E2PDO FRAME_B FULL_B/TCLAV GND GNT_B HGND HVDD3 IDSEL INITD INTR_B IRDY_B JCK JDI JDO JMS JRST_B OE_B PAR PAR3-PAR0 PAR64 PCI_MODE : Abort : Acknowledge 64-bit Transfer : Address/Data : Ground for Analog Part : Slave Address Select : Attention : +3.3 V Power Supply for Analog Part : Byte Enable : Control Memory Address : Local Port Byte Enable : Control Memory Data : Clock : Control Memory Output Enable : Control Memory parity : Control Memory Write Enable : Device Select : DMA Read/Write : PHY Empty/Rx Cell Available : Error : Clock for EEPROM : EEPROM Chip Select : Serial Data Input from EEPROM : Serial Data Output to EEPROM : Cycle Frame : PHY Buffer full/Tx Cell Available : Ground for Digital Part : Grant : Ground for High-Speed Part : +3.3 V Power Supply for High-Speed Part : ID Select : Initialization Disable : Interrupt : Initiator Ready : JTAG Test Pin : JTAG Test Pin : JTAG Test Pin : JTAG Test Pin : JTAG Test Pin : Output Enable : Parity : Bus Party : Parity 64 bits : PCI Mode Rx7-Rx0 SCLK SD SEL_B SERR_B SIZE2-SIZE0 SR/W_B STOP_B TCLK TDOC TDOT TENBL_B TEST TFKC TFKT TRDY_B TSOC Tx7-Tx0 VDD3 VDD5 PERR_B PHCE_B PHINT_B PHOE_B PHRST_B PHR/W_B PHYALM RCLK RCIC RCIT RDIC RDIT PDY_B REFCLK RENBL_B REQ64_B REQ_B RGND ROMCS_B ROMOE_B RSOC RST_B RVDD3 : Parity Error : PHY Chip Enable : PHY Interrupt : PHY Output Enable : PHY Reset : PHY Read/Write : Physical Alarm : Receive Clock : Receive Clock Input Complement : Receive Clock Input True : Receive Data Input Complement : Receive Data Input True : Target Ready : Reference Clock : Receive Enable : Request 64-bit Transfer : Request : Ground for Receive PLL Part : Expansion ROM Chip Select : Expansion ROM Output Enable : Receive Start Cell : Reset : +3.3 V Power Supply for Receive PLL Part : Receive Data Bus : SAR System Clock : Signal Detect : Slave Select : System Error : Burst Size : Slave Read /Write : Stop : Transmit Clock : Transmit Data Output Complement : Transmit Data Output True : Transmit Enable : Test Mode Pin : Transmit Reference Clock Complement : Transmit Reference Clock True : Target Ready : Transmit Start of Cell : Transmit Data Bus : +3.3 V Power Supply for Digital Part : +5 V Power Supply for Digital Part
ROMA15-ROMA0: Expansion ROM Address ROMD7-ROMD0 : Expansion ROM Input Data
PCBE7_B-PCBE0_B: Bus Command and Byte Enables
Data Sheet S12689EJ2V0DS00
5
PD98405
PIN CONFIGURATION
304-pin plastic QFP (0.5-mm fine pitch) (40 x 40 mm)
Generic Mode GND VDD3 AD24 BE3_B - AD23 GND VDD5 AD22 AD21 AD20 AD19 GND VDD3 AD18 AD17 AD16 BE2_B GND VDD5 SEL_B ASEL_B RDY_B SR/W_B GND VDD3 ABRT_B ERR_B - - GND VDD5 BE1_B AD15 AD14 AD13 GND VDD3 Generic Mode AD12 AD11 AD10 AD9 GND VDD5 AD8 BE0_B AD7 AD6 GND VDD3 AD5 AD4 AD3 AD2 GND VDD5 AD1 AD0 OE_B DR/W_B GND VDD3 SIZE2 SIZE1 SIZE0 PAR3 VDD5 GND PAR2 PAR1 PAR0 VDD3 - - - GND Generic Mode GND VDD3 - - VDD5 - - - - GND VDD3 - - - - GND VDD5 - - - - GND VDD3 - - - - GND VDD5 - - - - GND VDD3 - - - Generic Mode - - GND
No. 1 2 3 4 5 6 7 8 9
PCI Mode GND VDD3 AD24 PCBE3_B IDSEL AD23 GND VDD5 AD22
No.
PCI Mode
No.
PCI Mode
No.
PCI Mode
39 AD12 40 AD11 41 AD10 42 AD9 43 GND 44 VDD5 45 AD8 46 PCBE0_B 47 AD7 48 AD6 49 GND 50 VDD3 51 AD5 52 AD4 53 AD3 54 AD2 55 GND 56 VDD5 57 AD1 58 AD0 59 ACK64_B 60 REQ64_B 61 GND 62 VDD3 63 PCBE7_B 64 PCBE6_B 65 PCBE5_B 66 PCBE4_B 67 VDD5 68 GND 69 AD63 70 AD62 71 AD61 72 VDD3 73 AD60 74 AD59 75 AD58 76 GND
77 GND 78 VDD3 79 AD57 80 AD56 81 VDD5 82 AD55 83 AD54 84 AD53 85 AD52 86 GND 87 VDD3 88 AD51 89 AD50 90 AD49 91 AD48 92 GND 93 VDD5 94 AD47 95 AD46 96 AD45 97 AD44 98 GND 99 VDD3 100 AD43 101 AD42 102 AD41 103 AD40 104 GND 105 VDD5 106 AD39 107 AD38 108 AD37 109 AD36 110 GND 111 VDD3 112 AD35 113 AD34 114 AD33
115 AD32 116 PAR64 117 GND
118 PCI_MODE PCI_MODE 119 CD31 120 CD30 121 CD29 122 CD28 123 CD27 124 GND 125 VDD3 126 CD26 127 CD25 128 CD24 129 CD23 130 CD22 131 GND 132 CD21 133 CD20 134 CD19 135 CD18 136 CD17 137 GND 138 VDD3 139 CD16 140 CD15 141 CD14 142 CD13 143 CD12 144 CD11 145 GND 146 CD10 147 CD9 148 CD8 149 CD7 150 CD6 151 VDD3 152 GND CD31 CD30 CD29 CD28 CD27 GND VDD3 CD26 CD25 CD24 CD23 CD22 GND CD21 CD20 CD19 CD18 CD17 GND VDD3 CD16 CD15 CD14 CD13 CD12 CD11 GND CD10 CD9 CD8 CD7 CD6 VDD3 GND
10 AD21 11 AD20 12 AD19 13 GND 14 VDD3 15 AD18 16 AD17 17 AD16 18 PCBE2_B 19 GND 20 VDD5 21 FRAME_B 22 IRDY_B 23 TRDY_B 24 DEVSEL_B 25 GND 26 VDD3 27 STOP_B 28 PERR_B 29 SERR_B 30 PAR 31 GND 32 VDD5 33 PCBE1_B 34 AD15 35 AD14 36 AD13 37 GND 38 VDD3
6
Data Sheet S12689EJ2V0DS00
PD98405
No. PCI Mode Generic Mode GND VDD3 CD5 CD4 CD3 CD2 CD1 GND CD0 CPAR3 CPAR2 CPAR1 CPAR0 CA18 GND CA17 CA16 CA15 CA14 CA13 No. PCI Mode Generic Mode CBE3_B CBE2_B CBE1_B CBE0_B CWE_B COE_B INITD SCLK GND - - - - - - - - VDD3 - - No. PCI Mode Generic Mode GND - - - - - Rx7 Rx6 Rx5 Rx4 Rx3 Rx2 Rx1/TFKC Rx0/TFKT GND RCLK VDD3 RENBL_B RSOC EMPTY_B/ RCLAV/ RCIC FULL_B/ TCLAV/ RCIT TSOC TENBL_B GND TCLK VDD3 Tx7 Tx6 Tx5 Tx4 GND Tx3 Tx2 Tx1 Tx0 PHRST_B PHOE_B PHYALM/ PHR/W_B No. PCI Mode Generic Mode SD/ PHCE_B REFCLK/ PHINT_B AVDD3 AGND TEST HGND TDOT TDOC HVDD3 HVDD3 RDIC RDIT HGND RVDD3 JRST_B JCK JMS JDO JDI RGND
153 GND 154 VDD3 155 CD5 156 CD4 157 CD3 158 CD2 159 CD1 160 GND 161 CD0 162 CPAR3 163 CPAR2 164 CPAR1 165 CPAR0 166 CA18 167 GND 168 CA17 169 CA16 170 CA15 171 CA14 172 CA13
191 CBE3_B 192 CBE2_B 193 CBE1_B 194 CBE0_B 195 CWE_B 196 COE_B 197 INITD 198 SCLK 199 GND 200 ROMA15 201 ROMA14 202 ROMA13 203 ROMA12 204 ROMA11 205 ROMA10 206 ROMA9 207 ROMA8 208 VDD3 209 ROMA7 210 ROMA6
229 GND 230 ROMOE_B 231 E2PDI 232 E2PDO 233 E2PCLK 234 E2PCS 235 Rx7 236 Rx6 237 Rx5 238 Rx4 239 Rx3 240 Rx2 241 Rx1/TFKC 242 Rx0/TFKT 243 GND 244 RCLK 245 VDD3 246 RENBL_B 247 RSOC 248 EMPTY_B/ RCLAV/ RCIC 249 FULL_B/ TCLAV/ RCIT 250 TSOC 251 TENBL_B 252 GND
267 SD/ PHCE_B 268 REFCLK/ PHINT_B 269 AVDD3 270 AGND 271 TEST 272 HGND 273 TDOT 274 TDOC 275 HVDD3 276 HVDD3 277 RDIC 278 RDIT 279 HGND 280 RVDD3 281 JRST_B 282 JCK 283 JMS 284 JDO 285 JDI 286 RGND
173 CA12
CA12
211 ROMA5
-
287 VDD5
VDD5
174 GND 175 VDD3 176 CA11 177 CA10 178 CA9 179 CA8 180 CA7 181 CA6 182 GND 183 CA5 184 CA4 185 CA3 186 CA2 187 CA1 188 CA0 189 GND 190 VDD3
GND VDD3 CA11 CA10 CA9 CA8 CA7 CA6 GND CA5 CA4 CA3 CA2 CA1 CA0 GND VDD3
212 ROMA4 213 ROMA3 214 GND 215 ROMA2 216 ROMA1 217 ROMA0 218 ROMD7 219 ROMD6 220 ROMD5 221 ROMD4 222 ROMD3 223 ROMD2 224 ROMD1 225 ROMD0 226 ROMCS_B 227 VDD3 228 GND VDD3 GND GND
- -
288 INTR_B 289 RST_B 290 CLK 291 GNT_B 292 GND 293 VDD3 294 REQ_B 295 AD31 296 AD30 297 AD29 298 GND 299 VDD5 300 AD28 301 AD27 302 AD26 303 AD25 304 GND
INTR_B RST_B CLK GNT_B GND VDD3 REQ_B AD31 AD30 AD29 GND VDD5 AD28 AD27 AD26 AD25 GND
- - - - - - - - - - - -
253 TCLK 254 VDD3 255 Tx7 256 Tx6 257 Tx5 258 Tx4 259 GND 260 Tx3 261 Tx2 262 Tx1 263 Tx0 264 PHRST_B 265 PHOE_B 266 PHYALM/ PHR/W_B
Remark Open the pins to which no function is allocated (pins marked "-" in the Generic Mode column in the above table) in the Generic mode. Fix pin 5 (IDSEL) to the low/high level.
Data Sheet S12689EJ2V0DS00
7
PD98405
CONTENTS
1. PIN FUNCTIONS ............................................................................................................................... 1.1 PHY Layer Device Interface Signal ..........................................................................................
1.1.1 UTOPIA interface ........................................................................................................................... 1.1.2 PHY device control interface (external PHY mode, PHM of GMR register = 1) ............................. 1.2.1 Generic bus interface signals (PCI_MODE pin: low level)............................................................. 1.2.2 PCI bus interface signal (PCI_MODE pin: high level)....................................................................
9 9
9 11 12 15
1.2 Bus Interface Signals ................................................................................................................ 12
1.3 1.4 1.5 1.6 1.7 1.8
Control Memory Interface Signals ........................................................................................... PMD Interface Signals (internal PHY mode, PHM of GMR register = 0) ............................... JTAG Boundary Scan Signals .................................................................................................. Other Signals ............................................................................................................................. Power and Ground..................................................................................................................... Pin Status during and after Reset ............................................................................................
19 20 21 21 22 23
2. ELECTRICAL SPECIFICATIONS ..................................................................................................... 25 3. PACKAGE DRAWING ...................................................................................................................... 60 4. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 61
8
Data Sheet S12689EJ2V0DS00
PD98405
1. PIN FUNCTIONS
The package of the PD98405 has 304 pins. For details on how to use each pin, refer to PD98405 User's Manual (S12250E).
1.1 PHY Layer Device Interface Signal
The PHY Layer device interfaces include a UTOPIA interface by which the PD98405 exchanges ATM cells with a PHY device, and PHY control interface that is used to control a PHY device. The PD98405 supports two types of PHY layer device interfaces: UTOPIA octet and cell level. These modes are selected by setting the UOC bit of the GMR register. The PHY layer device interface signals are for an external PHY layer device. When using an internal PHY layer, open all the pins except the common pins. Even when the internal PHY layer is used, an external receive FIFO can be connected to the PD98405 via the UTOPIA interface. 1.1.1 UTOPIA interface (1/2)
Pin Name Rx7-Rx0 (Rx1 and Rx0: Shared with TFKC and TFKT) Pin No. 235-242 I/O I I/O Level TTL Function Receive data bus. These pins constitute an 8-bit input bus that inputs receive data from the network to the PD98405 from the PHY layer device in byte format. The PD98405 reads the data on this bus in synchronization with the rising edge of RCLK. Rx7 through Rx2 are internally pulled down. Open the pins of this bus when they are not used. Pull up Rx1 when it is not used, and pull down Rx0 when it is not used. Receive cell start position. This signal is input from the PHY layer device in synchronization with the first byte of cell data. It is high while the first byte of a header is input to Rx7 through Rx0. This signal is internally pulled down. Receive enable. This signal informs the PHY layer device that the PD98405 is ready to receive data in the next clock cycle.
RSOC
247
I
TTL
RENBL_B
246
O
TTL
Data Sheet S12689EJ2V0DS00
9
PD98405
(2/2)
Pin Name EMPTY_B/ RCLAV (shared with RCIC) Pin No. 248 I/O I I/O Level TTL Function PHY layer buffer empty/receive cell available. This signal informs the PD98405 that the PHY receive FIFO has no cell data to be transferred and that the PHY device cannot supply receive data. This signal functions as EMPTY_B when the UTOPIA interface is in the octet level handshake mode, to indicate that the data on Rx7 through Rx0 is invalid in the current clock cycle. In the cell level handshake mode, it functions as RCLAV, informing the PD98405 that no more cells are to be supplied after transfer of the current cell is completed. Pull down this pin when it is not used. Receive clock. This clock is used for synchronization when the PD98405 transfers cell data to and from the PHY layer device at the reception side. The SAR system clock input to the SCLK pin is output from this pin as is, immediately after the PD98405 has been reset. Transmit data bus. These pins form an 8-bit output bus that outputs data to be transmitted to the network, to the PHY layer device in byte format. The PD98405 outputs the data in synchronization with the rising edge of TCLK. Transmit cell start position. This signal is output in synchronization with the first byte of transmit cell data. Transmit enable. This signal informs the PHY layer device that data has been output to Tx7 through Tx0 in the current clock cycle. PHY layer buffer full/transmit cell available. The FULL_B signal informs the PD98405 that the input buffer of the PHY device is full and that the device can receive no more data. When the UTOPIA interface is in the octet level handshake mode, the PHY device inputs an inactive level as this signal if the device can receive cell data. In the cell level handshake mode, this signal functions as TCLAV, informing the PD98405 that the PHY device can receive the next single cell after transfer of the current cell is completed. Pull up this pin when it is not used. Transmit clock. This clock is used for synchronization when the PD98405 transfers cell data to and from the PHY layer device at the transmission side. The SAR system clock input to the SCLK pin is output as this clock as is.
RCLK
244
O
TTL
Tx7-Tx0
255-258, 260-263
O
TTL
TSOC
250
O
TTL
TENBL_B
251
O
TTL
FULL_B/ TCLAV (shared with RCIT)
249
I
TTL
TCLK
253
O
TTL
10
Data Sheet S12689EJ2V0DS00
PD98405
1.1.2 PHY device control interface (external PHY mode, PHM of GMR register = 1)
Pin Name PHR/W_B (shared with PHYALM) Pin No. 266 I/O O I/O Level TTL Function PHY read/write. The PD98405 indicates the PHY layer device control direction by using this pin. 1: Read 0: Write PHY layer output enable. The PD98405 enables output by the PHY layer device by making this signal low. PHY layer chip enable. The PD98405 makes this signal low when it accesses the PHY layer device. PHY layer interrupt. This pin inputs an interrupt signal to the PD98405 from the PHY layer device. The PHY layer device informs the PD98405 that it has an interrupt source by inputting a low level to this pin. Pull up this pin when it is not used. PHY layer reset. This signal is used to reset the PHY layer device. The PD98405 keeps this pin low for the duration of 17 clock cycles when a low level is input to the RST_B pin or when software reset is executed.
PHOE_B
265
O
TTL
PHCE_B (shared with SD) PHINT_B (shared with REFCLK)
267
O
TTL
268
I
TTL
PHRST_B
264
O
TTL
Caution The PHCE_B/SD pins are multiplexed pins and their functions differ depending on whether the internal PHY mode or external PHY mode is selected (by using the PHM bit of the GMR register). Because the PHCE_B/SD pins change the mode between input and output depending on the selected mode, be sure to correctly set the PHM bit of the GMR register.
Data Sheet S12689EJ2V0DS00
11
PD98405
1.2 Bus Interface Signals
The PD98405 supports a PCI bus interface or generic bus interface. Whether the PCI bus interface or generic bus interface is to be supported is selected by the PCI_MODE signal. The PCI bus interface can be directly connected to a PCI bus. The generic bus interface can be connected to a general I/O bus with a few circuits. 1.2.1 Generic bus interface signals (PCI_MODE pin: low level) (1/3)
Pin Name AD31-AD0 Pin No. 295-297, 300-303, 3, 6, 9-12, 15-17, 34-36, 39-42, 45, 47, 48, 51-54, 57-58 4 18 33 46 I/O I/O 3-state I/O Level TTL Function Address/data. These pins constitute a 32-bit address/data bus. They are input/output pins multiplexing an address bus and a data bus. An address is transferred at the first input/output clock. From the second clock and onward, data is transferred. When the PD98405 is not accessing the bus, the AD bus goes into a high-impedance state.
BE3_B BE2_B BE1_B BE0_B
O 3-state
TTL
Byte enable. These pins determine the byte that becomes valid in the master cycle of the PD98405. BE3_B corresponds to AD31 through AD24, and BE0_B corresponds to AD7 through AD0. BE3_B through BE0_B go into a high-impedance state when the PD98405 is not accessing a bus or when it is accessing a slave. Bus parity. These pins indicate the parity of AD31 through AD0. A parity check mode is set by the GMR register. Whether the parity is enabled or disabled, whether an odd parity or even parity is used, and whether a word parity or byte parity is used can be specified. When byte parity is used, PAR3 indicates the parity of AD31 through AD24, and PAR0 indicates the parity of AD7 through AD0. In the case of word parity, PAR2 through PAR0 do not function, and PAR3 serves as an input/output pin. These pins function as output pins when an address is output and when data is written, and as input pins when data is read. When the PD98405 is not accessing a bus, PAR3 through PAR0 go into a high-impedance state. Pull up these pins when they are not used.
PAR3 PAR2 PAR1 PAR0
66 69 70 71
I/O 3-state
TTL
OE_B
59
I
TTL
Output enable. When this pin is low, the PD98405 allows AD31 through AD0 and PAR3 through PAR0 to operate normally as three-state I/O pins. These pins go into a high-impedance state while a high level is input to this pin. Fix this pin to the low level in a system where the above pins do not have to forcibly go into a highimpedance state.
12
Data Sheet S12689EJ2V0DS00
PD98405
(2/3) Pin Name SIZE2 SIZE1 SIZE0 Pin No. 63 64 65 I/O O I/O Level TTL Function Burst size. These pins indicate the size of current DMA transfer. They are used to interface with a bus (such as S bus) that requires an explicit burst size.
SIZE2 0 0 0 0 1 1 Others
SIZE1 0 0 1 1 0 0
SIZE0 0 1 0 1 0 1
Function 1-word transfer 2-word burst 4-word burst 8-word burst 16-word burst 12-word burst Undefined
DR/W_B
60
O
TTL
DMA read/write. This pin indicates the direction of DMA access. 1: Read access 0: Write access Attention (DMA request). The PD98405 makes the ATTN_B signal low when it is to execute a DMA operation. The ATTN_B signal becomes inactive in synchronization with the rising edge of CLK when only one more word of data is to be transferred by means of DMA. Bus enable. The GNT_B signal goes low when the bus arbiter grants the PD98405 the bus mastership in response to a DMA request from the PD98405. When the PD98405 detects that the GNT_B signal has gone low, it starts a DMA operation, assuming that the bus mastership has been granted. Target device ready. This signal informs the PD98405 in the DMA cycle that the target device is ready for input/output. The PD98405 makes the RDY_B signal low if valid data exists on AD31 through AD0 when it executes a DMA read operation. When executing a DMA write operation, the PD98405 makes the ATTN_B signal low if the target device is ready for reception. The timing at which the PD98405 samples the RDY_B and ABRT_B signals can be bring forward by 1 clock depending on the setting of an internal register (GMR register).
ATTN_B
294
O
TTL
GNT_B
291
I
TTL
RDY_B
23
I
TTL
Data Sheet S12689EJ2V0DS00
13
PD98405
(3/3) Pin Name ABRT_B Pin No. 27 I/O I I/O Level TTL Function Abort. This signal is used to abort a data transfer cycle. If this signal goes low in the middle of a data transfer cycle, that cycle is aborted, and the PD98405 resumes burst starting from the aborted data. While a low level is input to ABRT_B, the RDY_B signal does not function. The user can bring forward the timing at which the PD98405 samples the RDY_B and ABRT_B signals by 1 clock (early mode) by using an internal register (GMR register). Pull up this pin when it is not used. System bus error. If an error is detected on the system bus, the device that manages the bus uses this pin to stop the operation by the PD98405. When a low level is input to this pin, the PD98405 stops all bus operations, sets the system bus error bit (bit 25) of the GSR register (when not masked), and generates an interrupt. Pull up this pin when it is not used. Slave read/write. This signal determines the direction of slave access. 1: Read access 0: Write access Slave select. This signal is asserted active (low) when slave access is selected for the PD98405. Make sure that the SEL_B signal goes low at the same time as or after the ASEL_B signal has gone low. In addition, insert an inactive period of two system clocks or more after the SEL_B signal has become inactive and before it becomes active next time. Slave address select. The ASEL_B signal selects the direct address register of the PD98405. When a low level is input to ASEL_B, the PD98405 samples the AD bus at the first rising edge of CLK. CLK 290 I TTL Clock. This is a system bus clock input pin. A clock of up to 33 MHz can be input. Reset. The RST_B signal initializes the PD98405 (on starting). After reset, the PD98405 can start normal operation. When a low level is input to RST_B, the internal state machine and registers of the PD98405 are reset, and all the three-state signals go into a high-impedance state. Reset input is asynchronous. If it is input during operation, the operation status at that time is lost. Keep RST_B low at least for the duration of one clock cycle. Interrupt output. Pull up this signal because it is an open-drain signal. This signal informs the CPU that an unmasked interrupt bit of the interrupt GSR register has been set.
ERR_B
28
I
TTL
SR/W_B
24
I
TTL
SEL_B
21
I
TTL
ASEL_B
22
I
TTL
RST_B
289
I
TTL
INTR_B
288
O
N-ch open-drain
14
Data Sheet S12689EJ2V0DS00
PD98405
1.2.2 PCI bus interface signal (PCI_MODE pin: high level) The PD98405 has a 32-/64-bit PCI bus interface. This bus interface can be directly connected to a PCI bus. In addition, the PD98405 also has a serial EEPROM interface and an expansion ROM interface. <1> PCI bus interface signals (1/2)
Pin Name AD31-AD0 Pin No. 295-297, 300-303, 3, 6, 9-12, 15-17, 34-36, 39-42, 45, 47, 48, 51-54, 57-58 4 18 33 46 I/O I/O 3-state I/O Level PCI Function Address/data. AD31 through AD0 constitute a 32-bit multiplexed address/data bus. When the PD98405 operates as a bus master, it drives an address at the first clock and transfers data at the second clock and onward.
PCBE3_B PCBE2_B PCBE1_B PCBE0_B
I/O 3-state
PCI
Bus command/byte enable. These signals define a "bus command" (bus transaction that occurs) in the address phase. In the data phase, they indicate which byte lane holds valid data. The PCBE3_B pin corresponds to byte 3 (bits 31 through 24), and PCBE0_B pin corresponds to byte 0 (bits 7 through 0). Parity. This signal indicates an even parity on the AD31 through AD0 and PCBE3_B through PCBE0_B pins, including the PAR signal. When the PD98405 is operating as a master, the PAR signal becomes active in the address and write data phases. When the PD98405 is operating as a target, this signal becomes active in the read data phase. Frame. This signal indicates the start and period of a bus transaction. When this signal is asserted active, it indicates the start of a bus transaction. While it is active, data is transferred. It is deasserted inactive when the next data transfer phase will transfer last data of the transaction. Target ready. This signal goes low when the target device is ready to complete the transaction of the current data. This signal is used in combination with IRDY_B, and read/write data transfer is executed when both IRDY_B and TRDY_B signals are low. Initiator ready. This signal goes low when the initiator is ready to complete the transaction of the current data. This signal is used in combination with TRDY_B, and read/write data transfer is executed when both IRDY_B and TRDY_B are low. If FRAME_B and IRDY_B are both inactive, the bus cycle is not executed. A wait cycle is inserted until both IRDY_B and TRDY_B are asserted active.
PAR
30
I/O 3-state
PCI
FRAME_B
21
I/O Sustained 3-state
PCI
TRDY_B
23
I/O Sustained 3-state
PCI
IRDY_B
22
I/O Sustained 3-state
PCI
Data Sheet S12689EJ2V0DS00
15
PD98405
(2/2)
Pin Name STOP_B Pin No. 27 I/O I/O Sustained 3-state I/O Sustained 3-state I/O Level PCI Function Stop. This signal goes low when the target device requests the master device to stop the current transaction. Device select. When the PD98405 is operating as a target, it makes this signal low after the FRAME_B signal has been asserted active and the PD98405 has recognized an address. When the PD98405 is operating as a master, it samples this signal to check to see if a target device has been selected. Initialization device select. This signal is high when the configuration register of the PD98405 is read or written. Request. The PD98405 makes this signal low to request the arbiter for the bus mastership. Grant. This signal goes low when the arbiter grants the PD98405 the bus mastership. Parity error. This signal indicates that the PD98405 has detected a data parity error. It is enabled when the "Parity Error Response" bit of the configuration register is set to "1". System error. This signal indicates that the PD98405 has detected an address parity error. It is enabled when both the "Parity Error Response" and "System Error Enable" bits of the configuration register are set to "1". Interrupt output. Pull up this signal because it is an open-drain signal. INTR_B informs the CPU that an unmasked interrupt bit of the interrupt GSR register has been set. Clock. This is a system bus clock input pin. A clock of up to 33 MHz is input. Reset. This signal initializes the PD98405 (on starting, etc.). When a low level is input to RST_B, the internal state machine and registers of the PD98405 are reset, and all the three-state signals go into a high-impedance state. The reset input is asynchronous. When this signal is input during operation, the operating status at that time is lost. Keep RST_B low at least for the duration of one clock cycle. After reset, do not access the PD98405 for the duration of at least 20 clocks.
DEVSEL_B
24
PCI
IDSEL
5
I
PCI
REQ_B
294
O
Note
PCI
GNT_B
291
I
PCI
PERR_B
28
I/O Sustained 3-state
PCI
SERR_B
29
O
N-ch open-drain
INTR_B
288
O
N-ch open-drain
CLK
290
I
PCI
RST_B
289
I
PCI
Note According to "PCI Local Bus Specification Revision 2.1", the REQ_B pin should go into a high-impedance state while a low level is input to the RST_B pin. The REQ_B pin of the PD98405, however, outputs a high level.
16
Data Sheet S12689EJ2V0DS00
PD98405
<2> PCI bus 64-bit expansion interface signals Open AD63 through AD32, PCBE7_B through PCBE4_B, and PAR64 when using the 32-bit PCI bus interface.
Pin Name AD63-AD32 Pin No. 69-71, 73-75, 79, 80, 82-85, 88-91, 94-97, 100-103, 106-109, 112-115 63 64 65 66 I/O I/O 3-state I/O Level PCI Function Address/data. AD63 through AD32 constitutes a 32-bit multiplexed address/data bus that extends the PCI bus to 64 bits. This address/data bus transfers the high-order 32 bits of a 64-bit address in the address phase. It outputs the high-order 32 bits of 64-bit data in the data phase when both REQ64_B and ACK64_B are asserted.
PCBE7_B PCBE6_B PCBE5_B PCBE4_B
I/O 3-state
PCI
Bus command/byte enable. These signals define a "bus command" (bus transaction that occurs) in the address phase. In the data phase, they indicate which byte lane holds valid data. The PCBE7_B pin corresponds to AD63 through AD56, and PCBE4_B pin corresponds to AD39 through AD32. Parity 64. This signal indicates an even parity on AD63 through AD32 and PCBE7_B through PCBE4_B pins, including the PAR64 signal. When the PD98405 is operating as a master, the PAR signal becomes active in the address and write data phases. When the PD98405 is operating as a target, it becomes active in the read data phase. Request 64. This signal indicates the start and period of a 64-bit bus transaction. When the PD98405 is operating as a master, it asserts REQ64_B active to request 64-bit data transfer. REQ64_B is the same as FRAME_B in timing. Acknowledge 64. When the PD98405 is operating as a target, it makes this signal low after the REQ64_B signal has been asserted active and the PD98405 has recognized an address. When the PD98405 is operating as a master, it samples this signal to check whether the target device has acknowledged 64-bit transfer. ACK64_B is the same as DEVSEL_B in timing.
PAR64
116
I/O 3-state
PCI
REQ64_B
60
I/O 3-state
PCI
ACK64_B
59
I/O Sustained 3-state
CPI
Data Sheet S12689EJ2V0DS00
17
PD98405
<3> Serial EEPROM interface signals The PD98405 has a serial EEPROM interface supporting MICROWIRETM interface. Through this serial EEPROM interface, the contents of the PCI configuration register can be loaded from an EEPROM connected. Remark It is recommended that National Semiconductor's "NM93C46" be connected as the EEPROM.
Pin Name E2PCS Pin No. 234 I/O O I/O Level TTL Function EEPROM chip select. This is a chip select signal for EEPROM. EEPROM data input. This signal is connected to the data output pin of the EEPROM. This signal is internally pulled down. E2PDO 232 O TTL EEPROM data output. This signal is connected to the data input pin of the EEPROM. EEPROM clock. This pin supplies the clock necessary for transferring data with the EEPROM. It divides the clock input to the CLK pin by 36 for output.
E2PDI
231
I
TTL
E2PCLK
233
O
TTL
<4> Expansion ROM interface signals. The PD98405 has an expansion ROM interface as option.
Pin Name ROMA15ROMA0 Pin No. 200-207, 209-213, 215-217 218-225 I/O O I/O Level TTL Function ROM address. These are address signals to access the 64K expansion ROM.
ROMD7ROMD0
I
TTL
ROM data. These are expansion ROM data signals and are internally pulled down. ROM select. This is a chip select signal for the expansion ROM. ROM output enable. This signal enables the output buffer of the expansion ROM during a read operation.
ROMCS_B
226
O
TTL
ROMOE_B
230
O
TTL
18
Data Sheet S12689EJ2V0DS00
PD98405
1.3 Control Memory Interface Signals
The control memory interface is used by the PD98405 to access the external control memory and external PHY layer device. This interface consists of a 19-bit address bus, a 32-bit data bus. The control memory of the host system can be accessed only through this interface.
Pin Name CD31-CD0 Pin No. 119-123, 126-130, 132-136, 139-144, 146-150, 155-159, 161 162-165 I/O I/O 3-state I/O Level TTL Function Control memory data. These three-state I/O pins constitute a 32-bit data bus that is used to transfer data to and from the control memory or PHY layer device. These signals are internally pulled down.
CPAR3CPAR0
I/O
TTL
Control memory parity. These signals indicate the parity of CD31 through CD0 every 8 bits. In the read cycle, the PD98405 checks the parity (when enabled). In the write cycle, it outputs the parity. These signals are internally pulled down. Control memory address. These signals constitute a 19-bit address bus that outputs an address to the control memory or PHY layer device during a read/write operation. Control memory write enable. This signal indicates the direction in which the control memory is accessed. 1: Read access 0: Write access Control memory output enable. This signal enables or disables data output of the control memory. Local port byte enable. These signals indicate the byte of the control port to be read or written. Initialization disable. This signal is used to disable automatic initialization of the control memory during chip test. Directly connect INITD to GND during normal operation other than test.
CA18-CA0
166, 168-173, 176-181, 183-188
O
TTL
CWE_B
195
O
TTL
COE_B
196
O
TTL
CBE3_BCBE0_B
191-194
O
TTL
INITD
197
I
TTL
Data Sheet S12689EJ2V0DS00
19
PD98405
1.4 PMD Interface Signals (internal PHY mode, PHM of GMR register = 0)
The PMD interface is used to connect a module such as an optical transceiver/receiver.
Pin Name RDIT Pin No. 278 I/O I I/O Level P-ECL True (+) P-ECL complement (-) P-ECL True (+) Function Receive serial data input. Pull up this pin when it is not used. Receive serial data input. Pull down this pin when it is not used.
RDIC
277
I
RCIT (shared with FULL_B)
249
I
Receive serial clock input. This pin is used when an external clock recovery/synthesizer is connected (PLL of GMR register = 1). Pull up this pin when it is not used. Receive serial clock input. This pin is used when an external clock recovery/synthesizer is connected (PLL of GMR register = 1). Pull down this pin when it is not used. Reference clock. This pin inputs a system clock (19.44 MHz) to the internal clock recovery/synthesizer. Pull up this pin when it is not used. Transmit serial data output.
RCIC (shared with EMPTY_B)
248
I
P-ECL complement (-)
REFCLK (shared with PHINT_B)
268
I
TTL
TDOT
273
O
P-ECL True (+) P-ECL complement (-) P-ECL True (+)
TDOC
274
O
Transmit serial data output.
TFKT (shared with Rx0)
242
I
Transmit serial clock input. This pin is used when an external clock recovery/synthesizer is connected (PLL of GMR register = 1). Pull up this pin when it is not used. Transmit serial clock input. This pin is used when an external clock recovery/synthesizer is connected (PLL of GMR register = 1). Pull down this pin when it is not used. PHY layer alarm detection signal. This signal is asserted active (high) when any of the internally monitored error statuses (CMDARM, LOS, OOF, LOF, LOP, OCD, LCD, Line AIS, Path AIS, Line RDI, and Path RDI) is detected. The error status to be reported can be selected by using the internal AMR1 and AMR2 registers. One or more error statuses can be selected. Signal detect. This pin inputs the signal detect signal (when LOS is detected, etc.) of the PMD device. When a low level is input to this pin, the PD98405 assumes LOS detection. Pull up this pin when it is not used.
TFKC (shared with Rx1)
241
I
P-ECL complement (-)
PHYALM (shared with PHR/W_B)
266
O
TTL
SD (shared with PHCE_B)
267
I
TTL
20
Data Sheet S12689EJ2V0DS00
PD98405
1.5 JTAG Boundary Scan Signals
Remark This function can be supported upon request. These signals conform to IEEE1149.1 JTAG Boundary-Scan Standard.
Pin Name JDI Pin No. 285 I/O I I/O Level TTL Function Boundary scan data input. Connect this pin to ground when it is not used. Boundary scan data output. Open this pin when it is not used. Boundary scan mode select. Connect this pin to ground when it is not used. Boundary scan clock input. Connect this pin to ground when it is not used. Boundary scan reset. Connect this pin to ground when it is not used.
JDO
284
O 3-state I
TTL
JMS
283
TTL
JCK
282
I
TTL
JRST_B
281
I
TTL
1.6 Other Signals
Pin Name SCLK Pin No. 198 I/O I I/O Level TTL Function SAR system clock. This pin supplies a clock for a SAR block operation. The maximum clock frequency is 25 MHz. PCI/generic bus mode. This pin selects PCI or generic bus mode. 0: Generic bus mode 1: PCI bus mode Internal test pin. Open this pin. When a high level is input to this pin, the test mode is selected. This signal is internally pulled down. The test mode is used for internal testing and cannot be used by the user.
PCI_MODE
118
I
TTL
TEST
271
I
TTL
Data Sheet S12689EJ2V0DS00
21
PD98405
1.7 Power and Ground
Pin Name VDD5 Pin No. 8, 20, 32, 44, 56, 67, 81, 93, 105, 287, 299 I/O - Function +5-V power (digital block). Supply +5 V to these pins when using the bus interface 5-V mode. In the 3.3-V mode, supply +3.3 V. +3.3-V power (digital block). These pins supply +3.3 V to the chip.
VDD3
2, 14, 26, 38, 50, 62, 72, 78, 87, 99, 111, 125, 138, 151, 154, 175, 190, 208, 227, 245, 254, 293 269
-
AVDD3
-
+3.3-V power (analog block). Supply power with a high quality to this pin by inserting a filter between AVDD3 and GND. +3.3-V power (high-speed block). Supply power with a high quality to this pin by inserting a filter between HVDD3 and HGND. +3.3-V power (receive PLL block). Supply power with a high quality to this pin by inserting a filter between RGND and this pin. Ground (digital block). These pins ground the chip.
HVDD3
275, 276
-
RVDD3
280
-
GND
1, 7, 13, 19, 25, 31, 37, 43, 49, 55, 61, 68, 76, 77, 86, 92, 98, 104, 110, 117, 124, 131, 137, 145, 152, 153, 160, 167, 174, 182, 189, 199, 214, 228, 229, 243, 252, 259, 292, 298, 304 270 272, 279 286
-
AGND HGND RGND
- - -
Ground (analog block) Ground (high-speed block) Ground (receive PLL block)
22
Data Sheet S12689EJ2V0DS00
PD98405
1.8 Pin Status during and after Reset
(1/2)
Pin Name RENBL_B RCLK Tx7-Tx0 TSOC TENBL_B TCLK PHR/W_B (external PHY)/PHYALM (internal PHY) PHOE_B PHCE_B (external PHY)/SD (internal PHY) AD31-AD0 PCBE3_B-PCBE0_B (PCI)/BE3_B-BE0_B (Generic) PAR FRAME_B TRDY_B IRDY_B STOP_B DEVSEL_B REQ_B (PCI)/ATTN_B (Generic) PERR_B SERR_B INTR_B AD63-AD61 (PCI)/PAR2-PAR0 (Generic) AD60-AD56 (PCI)/(Generic) AD55-AD32 (PCI)/(Generic) PCBE7_B-PCBE5_B (PCI)/SIZE2-SIZE0 (Generic) PCBE4_B (PCI)/PAR3 (Generic) PAR64 REQ64_B(PCI)/DR/W_B (Generic) E2PCS E2PDO E2PCLK ROMA15-ROMA0 ROMCS_B ROMOE_B CD31-CD0 CPAR3-CPAR0 CA18-CA0 During Reset 1 CLK output 0 0 0 CLK output 0 1 Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z (input) 1 Hi-Z (input) Hi-Z Hi-Z Hi-Z (input) Hi-Z (input)/Hi-Z (output) Hi-Z (input)/0 Hi-Z (input)/0 Hi-Z (input) Hi-Z (input) Hi-Z/1 0 0 0 0 1 1 0 0 0 After Reset 1 CLK output 0 0 0 CLK output 0 1 Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z (input) 1 Hi-Z (input) Hi-Z Hi-Z Hi-Z (input) Hi-Z (input)/Hi-Z (output) Hi-Z (input)/0 Hi-Z (input)/0 Hi-Z (input) Hi-Z (input) Hi-Z/1 0 0 0 0 1 1 0 0 0
Data Sheet S12689EJ2V0DS00
23
PD98405
(2/2)
Pin Name CWE_B COE_B TDOT TDOC JDO During Reset 1 1 Undefined Undefined Hi-Z After Reset 1 1 Undefined Undefined Hi-Z
Remark The internal PHY mode is set (PHM of GMR register = 0) after reset.
24
Data Sheet S12689EJ2V0DS00
PD98405
2. ELECTRICAL SPECIFICATIONS
* indicates changes from the Preliminary Data Sheet (document number: S12689E, 1st edition). Absolute Maximum Ratings
Parameter Supply voltage Symbol VDD VDD5 Input/output voltage
Note 1
Condition
Rating -0.5 to +4.6 -0.5 to +6.5
Unit V V V V V C C * * *
VI/VO
Normal I/O pin PCI I/O pin P-ECL pin
Note 2
-0.5 to +6.6 -0.5 to +6.6 -0.5 to +4.6 and VDD + 0.5 0 to +70 -65 to +150
Ambient operating frequency Storage temperature
TA Tstg
Notes 1. VDD5: Clamping diode-dedicated power supply 2. By supplying 5 V for clamping diode, the device can be protected from an 11-V reflection wave. Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the product(s). Be sure to use the product(s) within the ratings. Recommended Operating Conditions
Parameter Supply voltage Symbol VDD VDD5 VDD5 Ambient operating temperature High-level input voltage
Note
Condition
MIN. +3.0
TYP. +3.3 +3.3 +5.00
MAX. +3.6 +3.6 +5.25 +70 +5.5
Unit V V V C V
+3.3 V PCI +5 V PCI
+3.0 +4.75 0
Note
TA VIH1 Input pins other than PCI and P-ECL +5-V PCI pin +3.3-V PCI pin P-ECL pin Input pins other than PCI and P-ECL +5-V PCI pin +3.3-V PCI pin P-ECL pin
+2.0
VIH2 VIH3 VIH4 Low-level input voltage VIL1
+2.0 0.5 x VDD VDD - 1.49 0
VDD5 + 0.5 VDD + 0.5 VDD - 0.40 +0.8
V V V V
* * *
VIL2 VIL3 VIL4
-0.5 -0.5 VDD - 2.82
+0.8 0.3 x VDD VDD - 1.50
V V V *
Note VDD5: Clamping diode-dedicated power supply
Data Sheet S12689EJ2V0DS00
25
PD98405
DC Characteristics (TA = 0 to +70C, VDD = +3.3 V 0.3 V)
Parameter High-level output voltage Symbol VOH1 VOH2 VOH3 VOH4 Condition IOH = -3.0 mA
Note 1
MIN. +2.4
TYP.
MAX.
Unit V V V *
IOH = -500 A IOH = -2.0 mA
Note 2
(+3.3 V PCI) (+5 V PCI)
0.88 x VDD +2.4 VDD - 1.140 VDD - 0.690 0.144 x VDD
Note 2
RL = 50 , VT = VDD - 2 V (P-ECL) IOL = 9.0 mA
Note 1
V
*
Low-level output voltage
VOL1 VOL2 VOL3 VOL4 VOL5
V V V V V
*
IOL = 1500 A IOL = 3.0 mA IOL = 6.0 mA
Note 2
(+3.3 V PCI)
+0.4 +0.55 +0.55 VDD - 2.175 VDD - 1.755
Note 2
(+5 V PCI) (+5 V PCI)
Note 4
RL = 50 , VT = VDD - 2 V (P-ECL) fCLK = 33 MHz, normal operation VI = VDD VI = VDD or GND
*
Supply current Input leakage current (normal input) Input leakage current
Note 5
IDD II1 II2
650
900 10
mA
* * *
A A
28
160
Notes 1. VOH1 and VOL1 are applied to the following pins (output pins other than PCI): CD31-CD0, CPAR3-CPAR0, CA18-CA0, CBE3_B-CBE0_B, CWE_B, COE_B, JDO, RCLK, RENBL_B, TSOC, TENBL_B, TCLK, Tx7-Tx0, PHCE_B, PHOE_B, PHRW_B, E2PCS, E2PDO, E2PCLK 2. VOH2, VOH3, and VOL2 are applied to the following pins (PCI output pins): AD63-AD0, PCBE7_B-PCBE0_B, PAR, PAR64, REQ_B, INTR_B, FRAME_B, REQ64_B, TRDY_B, IRDY_B, DEVSEL_B, STOP_B, SERR_B, PERR_B 3. VOL3 is applied to the following pins (with +5-V PCI): AD31-AD0, PCBE3_B-PCBE0_B, PAR, REQ_B, INTR_B 4. VOL4 is applied to the following pins (with +5-V PCI): FRAME_B, TRDY_B, IRDY_B, DEVSEL_B, STOP_B, SERR_B, PERR_B, AD64-AD32, PCBE7_BPCBE4_B, ACK64_B, REQ64_B, PAR64 5. II2 is applied to the following pins: E2PDI, ROMD7-ROMD0, FULL_B, EMPTY_B, RSOC, Rx7-Rx0, CPAR3-CPAR0, CD31-CD0, PCI_MODE
26
Data Sheet S12689EJ2V0DS00
PD98405
Capacitance (TA = +25C, VDD = 0 V)
Parameter Input capacitance CLK input capacitance IDSEL input capacitance Output capacitance I/O capacitance Symbol CIN CCLK CIDSEL COUT CI/O 8 5 Condition MIN. TYP. MAX. 10 12 8 10 8 Unit pF pF pF pF pF
Internal pull-down resistor (TA = 0 to +70C, VDD = +3.3 V 0.3 V)
Parameter Internal pull-down resistance Symbol RPD Condition E2PDI, ROMD7-ROMD0, RSOC, Rx7-Rx2, CPAR3CPAR0, CD31-CD0, PCI_MODE MIN. 21.8 TYP. 37.1 MAX. 83.1 Unit k *
Data Sheet S12689EJ2V0DS00
27
PD98405
AC Characteristics (TA = 0 to +70C, VDD = +3.3 V 0.3 V, output pin load: 30 pF) CLK input (BUS interface clock - CLK pin)
Parameter CLK cycle time CLK high-level width CLK low-level width CLK slew rate Symbol tCYCLK tCLKH tCLKL slewCLK Condition MIN. 30 11 11 1 4 TYP. MAX. 125 Unit ns ns ns V/ns
2.4 V (MIN.) 2.0 V CLK 1.5 V 0.8 V tCLKH tCYCLK tCLKL 0.4 V (MAX.)
SCLK input (internal system clock - SCLK pin)
Parameter SCLK cycle time SCLK high-level width SCLK low-level width SCLK slew rate Symbol tCYSCLK tSCLKH tSCLKL slewSCLK Condition MIN. 40 15 15 1 4 TYP. MAX. 125 Unit ns ns ns V/ns
2.4 V (MIN.) 2.0 V SCLK 1.5 V 0.8 V tSCLKH tCYSCLK tSCLKL 0.4 V (MAX.)
RST input
Parameter RST low-level width RST slew rate Symbol tRSTL slewRST Condition MIN. tCYCLK 50 TYP. MAX. Unit ns V/ns
28
Data Sheet S12689EJ2V0DS00
PD98405
[MEMO]
Data Sheet S12689EJ2V0DS00
29
PD98405
PCI Bus Interface
Bus master read
Parameter CLK FRAME_B, REQ64_B valid time CLK FRAME_B, REQ64_B float time CLK AD (Address) valid time CLK AD (Address) float time AD (Data) setup time AD (Data) hold time CLK PCBE_B valid time CLK PCBE_B float time CLK IRDY_B valid time CLK IRDY_B float time TRDY_B setup time TRDY_B hold time DEVSEL_B, ACK64_B setup time DEVSEL_B, ACK64_B hold time STOP_B setup time STOP_B hold time CLK PAR valid time CLK PAR float time PAR setup time PAR hold time CLK PERR_B valid time CLK PERR_B float time Symbol tDFRAME Condition MIN. 1 TYP. MAX. 11 Unit ns *
tDFRAMEF
28
ns
*
tDADDR tDADDRF tSDATA tHDATA tDPCBE tDPCBEF tDIRDY tDIRDYF tSTRDY tHTRDY tSDEVSEL tHDEVSEL tSSTOP tHSTOP tDPAR tDPARF tSPAR tHPAR tDPERR tDPERRF
1
11 28
ns ns ns ns
*
8 1 1 11 28 1 11 28 8 1 8 1 8 1 1 11 28 8 1 1 11 28
* * *
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
* * * * * * * * *
* * *
30
Data Sheet S12689EJ2V0DS00
PD98405
Bus master read
CLK tDFRAMEF FRAME_B REQ64_B tDFRAME tDADDRF
tDADDR AD31-AD0
tSDATA (Data) tSDATA
tHDATA
(Address)
tHDATA (Data)
AD63-AD32 tDPCBE PCBE3_BPCBE0_B tDPCBE PCBE7_BPCBE4_B tDIRDY IRDY_B tSTRDY TRDY_B tSDEVSEL tDPARF (Output)
tDPCBEF
tDPCBEF
tDIRDYF
tHTRDY
tHDEVSEL
DEVSEL_B ACK64_B tDPAR PAR PAR64
tSPAR (Input)
tHPAR
tDPERR PERR_B
tDPERRF
CLK tHSTOP STOP_B tSSTOP
Data Sheet S12689EJ2V0DS00
31
PD98405
Bus master write
Parameter CLK FRAME_B, REQ64_B valid time CLK FRAME_B, REQ64_B float time CLK AD (Address) valid time CLK Data valid time CLK Data float time CLK PCBE_B valid time CLK PCBE_B float time CLK IRDY_B valid time CLK IRDY_B float time TRDY_B setup time TRDY_B hold time STOP_B setup time STOP_B hold time DEVSEL_B, ACK64_B setup time DEVSEL_B, ACK64_B hold time CLK PAR valid time CLK PAR float time PERR_B setup time PERR_B hold time Symbol tDFRAME Condition MIN. 1 TYP. MAX. 11 Unit ns *
tDFRAMEF
28
ns
*
tDADDR tDDATA tDDATAF tDPCBE tDPCBEF tDIRDY tDIRDYF tSTRDY tHTRDY tSSTOP tHSTOP tSDEVSEL tHDEVSEL tDPAR tDPARF tSPERR tHPERR
1 1
11 11 28
ns ns ns ns ns ns ns ns ns ns ns ns ns
* *
1
11 28
*
1
11 28
*
8 1 8 1 8 1 1 11 28 8 1
* * * * * * *
ns ns ns ns
* *
32
Data Sheet S12689EJ2V0DS00
PD98405
Bus master write
CLK tDFRAMF FRAME_B REQ64_B tDFRAME tDADDR AD31-AD0 (Address) tDDATA (Data) tDDATAF AD63-AD32 tDPCBE PCBE3_BPCBE0_B tDPCBE PCBE7_BPCBE4_B tDIRDY IRDY_B tSTRDY TRDY_B tSDEVSEL tDPAR PAR PAR64 (Output) (Output) tSPERR PERR_B tHPERR tHDEVSEL tHTRDY tDIRDYF tDPCBEF (Data) tDPCBEF tDDATAF
DEVSEL_B ACK64_B
tDPARF
CLK tHSTOP STOP_B tSSTOP
Data Sheet S12689EJ2V0DS00
33
PD98405
Target read
Parameter FRAME_B setup time FRAME_B hold time AD (Address) setup time AD (Address) hold time CLK AD (Data) valid time CLK AD (Data) float time PCBE_B setup time PCBE_B hold time IRDY_B setup time IRDY_B hold time CLK TRDY_B valid time CLK TRDY_B float time CLK STOP_B valid time CLK STOP_B float time CLK DEVSEL_B valid time CLK DEVSEL_B float time PAR setup time PAR hold time CLK PAR valid time CLK PAR float time PERR_B setup time PERR_B hold time Symbol tSFRAME tHFRAME tSADDR tHADDR tDDATA tDDATAF tSPCBE tHPCBE tSIRDY tHIRDY tDTRDY tDTRDYF tDSTOP tDSTOPF tDDEVSEL tDDEVSELF tSPAR tHPAR tDPAR tDPARF tSPERR tHPERR 8 1 8 1 1 11 28 1 1 8 1 8 1 1 11 28 11 28 11 28 Condition MIN. 8 1 8 1 1 11 28 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns * * * * * * * * * * * * * * * * * *
34
Data Sheet S12689EJ2V0DS00
PD98405
Target read
CLK tSFRAME FRAME_B tSADDR AD31-AD0 tSPCBE PCBE3_BPCBE0_B tSIRDY IRDY_B tDTRDYF tDTRDY TRDY_B tDDEVSELF tDDEVSEL DEVSEL_B tSPAR PAR
(Input)
(Address)
tHFRAME
tHADDR
tDDATA
tDDATAF (Data)
tHPCBE
tHIRDY
tHPAR
tDPAR
tDPARF (Output) tHPERR
PERR_B
tSPERR
CLK tDSTOPF STOP_B tDSTOP
Data Sheet S12689EJ2V0DS00
35
PD98405
Target write
Parameter FRAME_B setup time FRAME_B hold time AD (Address) setup time AD (Address) hold time AD (Data) setup time AD (Data) hold time PCBE_B setup time PCBE_B hold time IRDY_B setup time IRDY_B hold time CLK TRDY_B valid time CLK TRDY_B float time CLK STOP_B valid time CLK STOP_B float time CLK DEVSEL_B valid time CLK DEVSEL_B float time PAR setup time PAR hold time CLK PERR_B valid time CLK PERR_B float time Symbol tSFRAME tHFRAME tSADDR tHADDR tSDATA tHDATA tSPCBE tHPCBE tSIRDY tHIRDY tDTRDY tDTRDYF tDSTOP tDSTOPF tDDEVSEL tDDEVSELF tSPAR tHPAR tDPERR tDPERRF 8 1 1 11 28 1 1 Condition MIN. 8 1 8 1 8 1 8 1 8 1 1 11 28 11 28 11 28 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns * * * * * * * * * * * * * * * * *
36
Data Sheet S12689EJ2V0DS00
PD98405
Target write
CLK tSFRAME FRAME_B tHADDR tSADDR AD31-AD0 tSPCBE PCBE3_BPCBE0_B tSIRDY IRDY_B tDTRDYF tDTRDY TRDY_B tDDEVSELF tDDEVSEL DEVSEL_B tSPAR PAR
(Input)
(Address)
tHFRAME tSDATA tHDATA (Data) tHPCBE
tHIRDY
tHPAR (Input) tDPERRF tDPERR
PERR_B
CLK tDSTOPF STOP_B tDSTOP
Data Sheet S12689EJ2V0DS00
37
PD98405
Bus arbitration
Parameter CLK REQ_B valid time GNT_B setup time GNT_B hold time Symbol tDREQ tSGNT tHGNT Condition MIN. 1 10 1 TYP. MAX. 12 Unit ns ns ns * *
Bus arbitration
CLK tDREQ REQ_B tSGNT GNT_B tHGNT
38
Data Sheet S12689EJ2V0DS00
PD98405
Configuration read
Parameter FRAME_B setup time FRAME_B hold time AD (Address) setup time AD (Address) hold time CLK AD (Data) valid time CLK AD (Data) float time PCBE_B setup time PCBE_B hold time IDSEL setup time IDSEL hold time IRDY_B setup time IRDY_B hold time CLK TRDY_B valid time CLK TRDY_B float time CLK DEVSEL_B valid time CLK DEVSEL_B float time CLK PAR valid time CLK PAR float time PAR setup time PAR hold time PERR_B setup time PERR_B hold time Symbol tSFRAME tHFRAME tSADDR tHADDR tDDATA tDDATAF tSPCBE tHPCBE tSIDSEL tHIDSEL tSIRDY tHIRDY tDTRDY tDTRDYF tDDEVSEL tDDEVSELF tDPAR tDPARF tSPAR tHPAR tSPERR tHPERR 8 1 8 1 1 1 8 1 8 1 8 1 1 11 28 11 28 11 28 Condition MIN. 8 1 8 1 1 11 28 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns * * * * * * * * * * * * * * * * * *
Data Sheet S12689EJ2V0DS00
39
PD98405
Configuration read
CLK tHFRAME tSFRAME FRAME_B tSADDR AD31-AD0 tSPCBE PCBE3_BPCBE0_B tSIDSEL IDSEL tHIRDY tHIDSEL
(Address)
tHADDR
tDDATA
tDDATAF (Data)
tHPCBE
tSIRDY IRDY_B
tDTRDYF tDTRDY TRDY_B tDDEVSELF tDDEVSEL DEVSEL_B tSPAR PAR (Input) tHPAR tDPAR tDPARF (Output) tHPERR
tSPERR PERR_B
40
Data Sheet S12689EJ2V0DS00
PD98405
EEPROM interface
Parameter E2PCLK high-level width Symbol tWE2PCKLH Condition MIN. TYP. MAX. Unit ns
tCYCLK x 18 tCYCLK x 18 tCYCLK x 18 - 50 + 50 tCYCLK x 18 tCYCLK x 18 tCYCLK x 18 - 50 + 50
E2PCLK low-level width E2PCLK E2PCS valid time E2PCS E2PCLK E2PCLK E2PDO valid time E2PDI E2PCLK setup time E2PCLK E2PDI hold time E2PCS E2PDI (Status) valid delay time E2PCS E2PDI (Status) invalid delay time
tWE2PCLKL
ns
tDE2PCS tSE2PCS tDE2PDO tSE2PDI tHE2PDI tDE2PSTV
50 50 300 500 70 500
ns ns ns ns ns ns
tDE2PSTI
0
100
ns
EEPROM interface
tWE2PCLKH E2PCLK tDE2PCS E2PCS tDE2PDO E2PDO tSE2PDI E2PDI
(READ)
tWE2PCLKL
tSE2PCS
tDE2PCS
tHE2PDI
tDE2PSTV E2PDI
(Status)
tDE2PSTI (Status)
Data Sheet S12689EJ2V0DS00
41
PD98405
Expansion ROM interface
Parameter ROMOE_B ROMD valid time ROMCS_B ROMD valid time ROMA valid time ROMD valid time ROMOE_B ROMD float time ROMCS_B ROMD float time ROMA invalid time ROMD hold time Symbol tDROMOE tDROMCS tROMACC Condition ROMCS_B = VOL, ROMA valid ROMOE_B = VOL, ROMA valid ROMCS_B = ROMOE_B = VOL MIN. TYP. MAX. 200 200 200 Unit ns ns ns
tHROMOE tHROMCS tHROMA
ROMCS_B = VOL, ROMA valid ROMOE_B = VOL, ROMA valid ROMCS_B = ROMOE_B = VOL
0 0 0
ns ns ns
Expansion ROM interface
ROMCS_B
ROMOE_B
ROMA15ROMA0 tDROMOE ROMD7ROMD0 tDROMCS tHROMOE tHROMCS tROMACC tHROMA
42
Data Sheet S12689EJ2V0DS00
PD98405
Generic bus interface Slave write access
Parameter ASEL_B setup time ASEL_B hold time SEL_B setup time SEL_B hold time Address setup time Address hold time Data setup time Data hold time PAR setup time PAR hold time SR/W_B setup time SR/W_B hold time Symbol tSASEL tHASEL tSSEL tHSEL tSDADD tHDADD tSDDAT tHDDAT tSPAR1 tHPAR1 tSSRW tHSRW Condition MIN. 8 3 8 1 tCYCLK + 3 8 3 8 3 8 3 8 3 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns
Slave write access
CLK tSASEL ASEL_B tSSEL SEL_B tSDADD AD31-AD0 Address tSSRW SR/W_B tSPAR1 PAR3-PAR0 (Input) tHPAR1 tSPAR1 (Input) tHPAR1 tHSRW tHDADD tSDDAT Data tHDDAT tHSEL tHASEL
Data Sheet S12689EJ2V0DS00
43
PD98405
Slave read access
Parameter ASEL_B setup time ASEL_B hold time SEL_B setup time SEL_B hold time Address setup time Address hold time CLK data delay time CLK data float time PAR setup time PAR hold time CLK PAR delay time CLK PAR float time SR/W_B setup time SR/W_B hold time Symbol tSASEL tHASEL tSSEL tHSEL tSDADD tHDADD tDDDAT tFDDAT tSPAR1 tHPAR1 tDPAR1 tFPAR1 tSSRW tHSRW 2 8 3 2 8 3 18 18 Condition MIN. 8 3 8 1 tCYCLK + 3 8 3 18 18 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns * *
Slave read access
CLK tSASEL ASEL_B tSSEL SEL_B tSDADD AD31-AD0 Address (input) tSSRW SR/W_B tSPAR1 PAR3-PAR0 (Input) tHPAR1 tDPAR1 (Output) tFPAR1 tHSRW tHDADD tDDDAT Data (output) tFDDAT tHSEL tHASEL
44
Data Sheet S12689EJ2V0DS00
PD98405
DMA write access
Parameter CLK ATTN_B delay time GNT_B setup time GNT_B hold time CLK DR/W_B delay time CLK SIZE delay time CLK address delay time CLK address/data float time CLK BE_B delay time CLK BE_B float time CLK PAR delay time CLK PAR float time RDY_B setup time RDY_B hold time Symbol tDATTN tSGNT tHGNT tDDRW tDSIZE tDSADD tFSADD tDSBE tFSBE tDPAR2 tFPAR2 tSRDY tHRDY 2 8 3 2 2 8 3 2 2 18 18 18 18 18 18 18 18 Condition MIN. TYP. MAX. 18 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns * * * * *
Data Sheet S12689EJ2V0DS00
45
46
Data Sheet S12689EJ2V0DS00
DMA write access (Example: 2-word burst)
CLK tDATTN ATTN_B tSGNT GNT_B tDDRW DR/W_B tDSIZE SIZE2-SIZE0 tDSADD AD31-AD0
Address (output)
tDATTN
tHGNT
tDDRW
tDSIZE
tFSADD Data 0 (output) tDSBE Data 1 (output)
tFSADD
tFSBE BE 0 (output) tSRDY BE 1 (output) tHRDY
BE3_B-BE0_B
RDY_B (Normal mode) tSRDY RDY_B (Early mode) tDPAR2 PAR3-PAR0
(Output)
tHRDY
tFPAR2
(Output)
tDPAR2
(Output)
PD98405
PD98405
DMA read access
Parameter CLK ATTN_B delay time GNT_B setup time GNT_B hold time CLK DR/W_B delay time CLK SIZE delay time CLK address delay time CLK address/data float time CLK BE_B delay time CLK BE_B float time CLK PAR delay time RDY_B setup time RDY_B hold time Data setup time Data hold time PAR setup time PAR hold time Symbol tDATTN tSGNT tHGNT tDDRW tDSIZE tDSADD tFSADD tDSBE tFSBE tDPAR2 tSRDY tHRDY tSSDAT tHSDAT tSPAR2 tHPAR2 8 3 8 3 8 3 2 2 8 3 2 2 18 18 18 18 18 18 18 Condition MIN. TYP. MAX. 18 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns * * * *
Data Sheet S12689EJ2V0DS00
47
48
DMA read access (Example: 2-word burst)
CLK tDATTN ATTN_B tSGNT GNT_B tDDRW DR/W_B
Data Sheet S12689EJ2V0DS00
tDATTN
tHGNT
tDDRW
tDSIZE SIZE2-SIZE0 tDSADD AD31-AD0
Address (output)
tDSIZE
tFSADD
tSSDAT Data 0 (input)
tHSDAT Data 1 (input) tFSBE
tDSBE BE3_B-BE0_B BE 0 (output) tSRDY RDY_B (Normal mode) tSRDY RDY_B (Early mode) tDPAR2 PAR3-PAR0
(Output)
BE 1 (output) tHRDY
tHRDY
tSPAR2
(Input)
tHPAR2
(Input)
PD98405
PD98405
ABRT_B, ERR_B, and OE_B pins
Parameter ABRT_B setup time ABRT_B hold time ERR_B setup time ERR_B hold time OE_B AD/PAR output determination time OE_B AD/PAR high-impedance determination time Symbol tSABRT tHABRT tSERR tHERR tDADOE Condition MIN. 8 3 8 3 18 TYP. MAX. Unit ns ns ns ns ns
tFADOE
18
ns
DMA abort/ERR_B timing
CLK
ATTN_B
GNT_B tSABRT ABRT_B tHABRT
tSERR ERR_B
tHERR
OE_B timing
tFADOE AD31-AD0 PAR3-PAR0 Data 0 (output) tDADOE Data 0 (output)
OE_B
Data Sheet S12689EJ2V0DS00
49
PD98405
UTOPIA interface (external PHY mode) Transmission operation
Parameter SCLK TCLK delay time TCLK Tx delay time TCLK TSOC delay time TCLK TENBL_B delay time FULL_B setup time FULL_B hold time Symbol tDTCLK tDTX tDTSOC tDTEN tSFULL tHFULL 2 2 2 8 1 Condition MIN. TYP. MAX. 15 18 13.62 13.66 Unit ns ns ns ns ns ns * * * *
Reception operation
Parameter SCLK RCLK delay time Rx setup time Rx hold time RSOC setup time RSOC hold time RCLK RENBL_B delay time EMPTY_B setup time EMPTY_B hold time Symbol tDRCLK tSRX tHRX tSRSOC tHRSOC tDREN tSEMPT tHEMPT 8 1 8 1 2 8 1 13.63 Condition MIN. TYP. MAX. 15 Unit ns ns ns ns ns ns ns ns * *
SCLK
TCLK
tDTCLK
SCLK
RCLK
tDRCLK
50
Data Sheet S12689EJ2V0DS00
UTOPIA interface (1) Transmission timing
TCLK tDTX
Tx7-Tx0
H1
H2
H3
H4
`00H'
P1
Invalid
P2
P3
P4
P5
P6
P7
P8
P9
Data Sheet S12689EJ2V0DS00
TSOC tDTSOC tDTSOC tDTEN
tDTEN
TENBL_B
tSFULL FULL_B
tHFULL
H1-H4: ATM header P1-P9: Payload data
PD98405
51
52
UTOPIA interface (2) Reception timing
RCLK tSRX tHRX Rx7-Rx0
Data Sheet S12689EJ2V0DS00
H1
H2
H3
Invalid
H4
H5
P1
P2
Invalid
P3
P4
P5
P6
P7
RSOC tHRSOC tDREN
tSRSOC RENBL_B
tDREN
tSEMPT EMPTY_B
tHEMPT
H1-H4: ATM header P1-P7: Payload data
PD98405
PD98405
Control memory access Write
Parameter CA CWE_B setup time CBE_B CWE_B setup time CWE_B low-level width CWE_B CD float time CWE_B COE_B delay time CA hold time (vs CWE_B ) CBE_B hold time (vs CWE_B ) CD output time (vs CWE_B ) CWE_B CPAR float time CPAR output time (vs CWE_B ) Symbol tSCWE tSCWE2 tCWEL tFCD Condition MIN. 0 0 1 tSCLKL - 2 0 1 tSCLKL + 8.59 TYP. MAX. Unit ns ns ns ns *
tDCOE tHCA tHCBE tSCD tFCPAR
0 0 0 15 0 1 tSCLKL + 8.65
ns ns ns ns ns * *
tSCPAR
15
ns
*
Write timing
SCLK
CBE3_BCBE0_B tSCWE2 tHCBE
CA18-CA0 tSCWE CWE_B tDCOE COE_B tSCD CD31-CD0 (Output) tSCPAR CPAR3-CPAR0 (Output) tFCPAR tFCD tCWEL tHCA
Data Sheet S12689EJ2V0DS00
53
PD98405
Read
Parameter Permissible CD delay time (vs CBE_B ) Permissible CD delay time (vs CA) Symbol tDCDCB Condition MIN. TYP. MAX. 1 tCYSCLK - 18 1 tCYSCLK - 18 1 tCYSCLK - 18 0 0 0 1 tCYSCLK - 18 1 tCYSCLK - 18 1 tCYSCLK - 18 0 0 0 Unit ns *
tDCDCA
ns
*
Permissible CD delay time (vs COE_B ) CD hold time (vs CBE_B ) CD hold time (vs CA) CD hold time (vs COE_B ) Permissible CPAR hold time (vs CBE_B ) Permissible CPAR hold time (vs CA)
tDCDCO
ns
*
tHCDCB tHCDCA tHCDCO tDCPCB
ns ns ns ns *
tDCPCA
ns
*
Permissible CPAR hold time (vs COE_B ) CPAR hold time (vs CBE_B ) CPAR hold time (vs CA) CPAR hold time (vs COE_B )
tDCPCO
ns
*
tHCPCB tHCPCA tHCPCO
ns ns ns
54
Data Sheet S12689EJ2V0DS00
PD98405
Read timing
SCLK
CBE3_BCBE0_B
CA18-CA0
CWE_B
"H"
COE_B tDCDCB tDCDCA tDCDCO CD31-CD0 (Input) tHCDCB tHCDCA tHCDCO
CPAR3-CPAR0 tDCPCO tDCPCA tDCPCB
(Input) tHCPCO tHCPCA tHCPCB
Data Sheet S12689EJ2V0DS00
55
PD98405
PHY status access Write
Parameter SCLK CA delay time SCLK PHRW_B delay time SCLK PHCE_B delay time SCLK CD delay time PHCE_B CD float time Symbol tDPCA tDPHRW tDPHCE tDPCD tFPCD 1 tCYSCLK - 10 Condition MIN. TYP. MAX. 20 20 20 23 1 tCYSCLK + 10 Unit ns ns ns ns ns *
Write timing
1 clock SCLK tDPCA CA18-CA0 tDPHRW PHRW_B tDPHCE PHCE_B tDPHCE tDPHRW tDPCA 4 clocks 1 clock
PHOE_B
"H" tDPCD tFPCD (Output)
CD31-CD0
Read
Parameter CD setup time CD hold time SCLK CA delay time SCLK PHRW_B delay time SCLK PHCE_B delay time SCLK PHOE_B delay time Symbol tSPCD tHPOECD tDPCA tDPHRW tDPHCE tDPHOE Condition MIN. 10 0 20 20 20 20 TYP. MAX. Unit ns ns ns ns ns ns *
56
Data Sheet S12689EJ2V0DS00
Read timing
1 clock 6 clocks 5 clocks 4 clocks
SCLK tDPCA CA18-CA0 tDPHRW PHRW_B tDPHCE PHCE_B tDPHOE PHOE_B tSPCD CD31-CD0 (Input) tHPOECD tDPHOE tDPHCE tDPCA
Data Sheet S12689EJ2V0DS00
PD98405
57
PD98405
PMD serial interface (internal PHY mode)
Parameter REFCLK cycle time REFCLK high-level width Symbol tCYRF tWRFH Condition MIN. -20 ppm 0.4 x tCYRF 0.4 x tCYRF TYP. 51.4403 MAX. +20 ppm 0.4 x tCYRF 0.4 x tCYRF Unit ns ns * *
REFCLK low-level width
tWRFL
ns
*
REFCLK
tWRFH tCYRF
tWRFL
58
Data Sheet S12689EJ2V0DS00
PD98405
Others
Parameter SEL_B recovery time SEL_B GNT_B recovery time RDY_B SEL_B recovery time Symbol tRVSEL tRVSM tRVMS RDY_B mode during normal operation Condition MIN. 2 1 1 TYP. MAX. Unit tCYCLK tCYCLK tCYCLK
RST_B input pulse width RST_B SEL_B recovery time
tRSTL tRSTSL
1 20
tCYCLK tCYCLK
Others timing
CLK
SEL_B tRVSEL GNT_B tRVMS RDY_B
tRVSM
tRSTL
RST_B tRSTSL
SEL_B
Data Sheet S12689EJ2V0DS00
59
PD98405
3. PACKAGE DRAWING
304 PIN PLASTIC QFP (FINE PITCH) (40x40)
A B
228 229 153 152
detail of lead end S C D Q R
304 1
77 76
F G P H I J
M
K M NS L S
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 42.60.2 40.00.2 40.00.2 42.60.2 1.25 1.25 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.30.2 0.50.2 0.145 +0.055 -0.045 0.10 3.70.1 0.40.1 55 4.3 MAX.
NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.
P304GL-50-NMU, PMU-3
60
Data Sheet S12689EJ2V0DS00
PD98405
4. RECOMMENDED SOLDERING CONDITIONS
Solder this product under the following recommended conditions. For details of the recommended soldering conditions, refer to information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended, consult NEC. Surface-mount type
* PD98405GL-PMU: 304-pin plastic QFP (0.5-mm fine pitch) (40 x 40 mm)
Recommended Conditions Symbol IR35-203-1
Soldering Method(s) Infrared reflow
Soldering Conditions Package peak temperature: 235C, Time: 30 sec max. (210C min.), Note Number of times: once, Number of days: 3 (after that, prebaking is necessary at 125C for 20 hours)
Partial pin heating
Pin temperature: 300C max., Time: 3 sec. Max. (per device side)
-
Note Number of days in storage after the dry pack has been opened. The storage conditions are at 25C, 65% RH MAX.
Data Sheet S12689EJ2V0DS00
61
PD98405
[MEMO]
62
Data Sheet S12689EJ2V0DS00
PD98405
[MEMO]
Data Sheet S12689EJ2V0DS00
63
PD98405
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98. 8

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